The present invention relates to a development of a semiconductor chip; and, more particularly, to a micro controller development system (MDS) capable of helping a development of hardware and related software of a micro control unit (MCU).
To test a manufactured micro control unit (MCU) or develop the MCU for a special function, a micro controller development system (MDS) has been usually used. Recently, a very large scale integration (VLSI) is rapidly developed and most of recently designed MCUs have a plurality of code read only memories (ROMs) with the development of integration.
Therefore, the MDS may make it possible to fetch a program to be transplanted to a code ROM of the MCU from an external ROM or a random access memory (RAM).
FIG. 1A is a circuit diagram illustrating a conventional MDS and FIG. 1B is a timing diagram showing each signal of the MDS in FIG. 1A. The MCU contains an optional Eva-chip for carrying out a fetch function, which transplants a program from an external ROM and RAM to the code ROM in the MCU. The Eva-chip is an additional chip for an I/O interface for address and command signals needed in transplanting data to a code ROM in the MCU.
Referring to FIGS. 1A and 1B, the MDS includes a MCU chip 10 and a memory 20, such as a ROM or a RAM, to store commands for transplanting a program to a code ROM in the MCU chip 10. The MCU chip 10 has data input units 11a and 11b and data output units 12a and 12b for a data processing with an external device (not shown) and further has a command input unit 13. The data are inputted and outputted by the data input units 11a and 11b and the data output units 12a and 12b via data I/O pins 12 and 18 of the MCU chip 10.
On the other hand, when a program is transplanted to the code ROM, the MCU chip 10 outputs an n-bit address signal ADD to the memory 20 through an address bus and the memory 20 outputs a p-bit command signal, which corresponds to the address signal ADD, to the MCU chip 10 after a predetermined access time (tACC) in response to a control signal outputted from the MCU chip 10. The outputted command signal is sampled to a MCU internal command bus by a command input unit 13, being synchronized with a control signal IO2Inst.
At this time, the MCU 10 used in MDS needs a pin 14 for outputting the n-bit address ADD to transplant data to the code ROM, a pin 19 for inputting the p-bit command (Inst) and a control signal output pin 16 for controlling the memory 20 as well as the data I/O pins 12 and 18 for the data input and output.
As above described, a conventional MDS needs not only an I/O port but also an additional port (Eva-chip) for transplanting a program to a code ROM within the MCU. Because of the additional port, it is difficult to simplify the structure of the MDS so a development cost is increased and an operation time is extended.
It is, therefore, an object of the present invention to provide a micro controller development system capable of employing an data I/O port of the MCU as a port for transplanting a program to a ROM within a micro control unit.
Another object of the present invention is to provide a micro controller development system (MDS) capable of preventing a collision between an inputted data and an outputted data.
In accordance with an aspect of the present invention, there is provided a micro controller development system, comprising: a micro controller including first and second data I/O ports; a memory unit for storing commands for a program to be transplanted to an internal code ROM in the micro controller; a switching means for transferring address signals to the memory unit in response to a first control signal and for transferring the commands from the memory unit to the micro controller in response to the first control signal, wherein the address signals are transferred via the first data I/O port and wherein the commands are transferred via the second data I/O port; a first I/O interface unit for performing data input or output between the first data I/O port and a single data port of an external device in response to a second control signal; and a second I/O interface unit for performing data input or output between the second data I/O port and the single data port external device in response to the second control signal.